Integrated circuits use conductive interconnects to wire together the individual devices on a semiconductor substrate, or to communicate externally to the integrated circuit. Interconnect metallization for vias and trenches may include aluminum alloys and copper. Electro-migration (EM) is a well-known reliability problem for metal interconnects, caused by electrons pushing and moving metal atoms in the direction of current flow at a rate determined by the current density. Electro-migration can eventually lead to the thinning of the metal line, which can result in higher resistivity or, worst case, a metal line breakage. Fortunately, not every interconnect metal line on an IC has current moving in the same direction all the time, as it mostly does in power supply and ground lines. However, as metal lines get narrower (International Technology Roadmap for Semiconductors (ITRS) calls for a ˜0.7× reduction in the line width for every technology node), electro-migration becomes more of an issue.
In aluminum lines, EM is a bulk phenomenon and is well controlled by the addition of small amounts of a dopant, such as copper. EM in copper lines, on the other hand, is a surface phenomenon. It can occur wherever the copper is free to move, typically at an interface where there is poor adhesion between the copper and another material. In today's dual-damascene process, this happens most often on the top of the copper line where it interfaces with what is typically a SiC diffusion barrier layer, but it can also happen at the copper/barrier interface. With each migration to the next technology node, and resulting increase in current density, the problem worsens.
The solution to EM problems, as well as related stress voids, another common reliability problem, has been a story of process integration: optimized depositions (i.e. reducing thickness of barrier and seed layers), pre- and post-deposition wafer cleanings, surface treatments, etc., all aimed at providing homogeneous surfaces and good adhesion between layers to minimize metal atom migration and void propagation. In the dual-damascene process, trenches and holes (for contacts and vias) are etched in the dielectric, then lined with a barrier material, such as tantalum (Ta), tantalum nitride (TaN), or a combination of both films, followed by the deposition of a copper seed layer, copper electroplating, copper planarization using CMP and then deposition of a dielectric stack, such as SiC/low-k/SiC. Since an oxide readily forms on copper when copper is exposed to air, proper post-CMP cleaning and removal of the copper oxide before capping the copper with SiC is required to ensure good adhesion between copper and SiC. Removal of the copper oxide prior to the SiC deposition is essential to good EM performance and reducing resultant metal resistivity.
Recently, capping Copper with a cobalt-alloy capping layer, such as CoWP (cobalt tungsten phosphide), CoWB (cobalt tungsten boride), or CoWBP (cobalt tungsten boro-phosphide), before the SiC dielectric barrier layer, has been shown to significantly improve electro-migration, compared to SiC over copper. FIG. 1 shows that the cobalt-alloy capping layers 20, 30 are deposited over copper layers 23, 33 and under dielectric capping SiC layers 25, 35, respectively. Ta and/or TaN barrier layers are illustrated as layers 24, 34. The cobalt-alloy layers 20, 30 improve the adhesion between copper 23, 33 and SiC cap layers 25, 35. The cobalt-alloy layers 20, 30 can also exhibit certain copper diffusion barrier characteristics. The cobalt-alloy capping layers can be selectively deposited on copper by electroless deposition. However, the electroless deposition can be inhibited by thin copper oxide layer, which can be formed when copper is exposed to air. Further, contaminants on the copper and dielectric surfaces can cause pattern-dependent plating effects include pattern-dependent thickness of the Co alloy, as well as pattern-dependent copper line thickness loss in part due to etching during the ‘incubation’ time required to initiate the Co plating reaction. Therefore, it is important to control the processing environment to limit (or control) the growth of native copper oxide, and to remove copper oxide and organic contaminants on the copper surface and organic and metallic contaminants on the dielectric surface immediately prior to depositing the metallic capping layer, such as a cobalt-alloy. Further, to reduce pattern-dependent deposition variability, the dielectric surface must be controlled to normalize its influence across structures of different pattern densities. Engineering the metal-to-metal interface between the copper layers 23, 33, between copper and barrier layers 33 and 34, 23 and 24, and the adhesion promoting layers (or metallic capping layers), such as the cobalt-alloy layers 20, 20, is very critical in ensuring good interfacial adhesion and good EM performance. Further, as metal lines become narrower, physical vapor deposition (PVD) barrier and seed films form a larger part of the metal line, increase the effective resistivity, and hence current density. Thin and conformal barrier and seed layers can mitigate this trend, with atomic layer deposition (ALD) barriers (TaN, Ru or hybrid combinations) providing conformal step coverage and acceptable barrier properties, and electroless Cu process providing a conformal seed layer. Until now, however, there is no electroless Cu seed layer that can adhere to the ALD TaN barrier films produced.
In view of the foregoing, there is a need for systems and processes that produce a metal-to-metal interface with improved electro-migration performance, low sheet resistance, and improved interfacial adhesion for copper interconnects.